Embedded flash memories are typically integrated into a system chip such as a subscriber identity module (SIM) card chip or a smart card chip in form of an intellectual property (IP) core. Thus, the embedded flash memories are different from stand-alone flash memory products due to their embedded feature.
An embedded flash memory array typically uses the NOR structure (as shown in FIG. 1) to ensure random access operation. A bit line (BL) shown in FIG. 1 is used to control a voltage of a drain of a transistor. A word line (WL) is used to control a voltage of a gate of the transistor. A source line is used to control a voltage of a source of the transistor. In the circuit shown in FIG. 1, any one of flash memory cells in the flash memory array can be read by controlling the bit line, word line and source line together. Taking a NMOS flash memory for example, if it is required to read out data stored in a flash memory cell marked by a circle shown in FIG. 1, the word line corresponding to the marked flash memory cell is pulled up (the other word lines are grounded), the bit line corresponding to the marked flash memory cell is pulled up (the other bit lines are grounded), and all the source lines are grounded. Correspondingly, only data stored in the marked flash memory cell can be read out, while the other flash memory cells can not output data due to the grounded gates or a zero-voltage difference between their bit line and source line.
U.S. Pat. No. 5,912,842 discloses a 2-transistor (2T) positive metal oxide semiconductor (PMOS) flash memory. A flash memory cell for storing data in the 2T PMOS flash memory includes a select gate PMOS transistor and a control gate PMOS transistor having a floating gate, and the two transistors are coupled in series.
The PMOS transistor is an elementary device for the modern very large scale integrated (VLSI) circuits. The PMOS transistor typically has four control nodes including a gate node, a drain node, a source node and a bulk node. The transistor can be turned on or off by controlling the voltages applied to these four nodes. The select gate transistor is typically coupled in series with the control gate transistor to form a 2T flash memory cell. The operation on the 2T flash memory cell with a specific address can be selected or cancelled by controlling the select gate transistor. The control gate transistor is a cell that stores “0/1”. For example, specific operations may be performed onto the transistor such that it may have different electric characteristics (e.g., different threshold voltages) representing “0” or “1”, respectively. The floating gate is usually embedded between the control gate and the silicon substrate of the control gate transistor to form a sandwich structure. In the embedded 2T PMOS flash memory, the floating gate and the control gate are separated by an oxide-nitride-oxide dielectric film, and the floating gate and the silicon substrate are separated by an oxide dielectric film. The floating gate is N-type or P-type doped polysilicon in which charges can be stored so as to change the electric characteristics of the control gate PMOS transistor.
An erase operation generally refers to an operation for “erasing data” in the flash memory products. For the embedded PMOS flash memories of the present invention, the erase operation generally utilizes the Fowler-Nordheim (FN) tunneling effect to discharge the electrons stored within the floating gate to increase the threshold voltage of the control gate transistor, such that the flash memory cell operated presents data “1” when read by an external circuit.
A program operation generally refers to an operation for “programming data” in the flash memory products. For the embedded PMOS flash memories of the present invention, the program operation generally uses the band-band hot electron injection (BBHE) effect to inject electrons into the floating gate to lower the threshold voltage of the control gate transistor, such that the flash memory cell operated presents data “0” when read by the external circuit.
An erase disturb refers that, when data associated with certain address is erased, data associated with some other addresses are mistakenly changed.
A read disturb refers to that, when data associated with certain address is read, data associated with some other addresses are mistakenly changed.
A program disturb refers to that, when data associated with certain address is programmed, data associated with some other addresses are mistakenly changed.
In order to perform the erase, read or program operation onto the flash memory products, it is required to make the operating conditions match with the characteristics of the devices, satisfy with the performance of the devices and avoid negative influence on the reliability of the flash memory products. A lot of time and financial cost, as well as fully considering the influence of factors including chip production process, chip circuit design, chip device characteristics, chip quality and chip costs, are required to determine a set of optimal operating conditions.